The present invention relates to electrical circuits susceptible to noise and, more specifically, to means for eliminating noise effects on susceptible circuits.
Integrated circuits are increasingly using both digital and analog circuits on the same monolithic die. As the integration density and switching speeds of noisy digital circuits continue to increase with technological advancements so do the noise levels and the adverse effects of noise on susceptible circuits. Consequently, the integration of analog or other noise susceptible circuitry with high speed digital logic is becoming increasingly difficult.
Switching noise from logic circuits is coupled into noise susceptible circuits through the integrated circuit substrate and power lines. Switching noise can have a serious performance impact on noise susceptible circuits. Noise problems range from analog circuits running out of specification to more severe problems such as erratic circuit operation.
Clock distribution systems, the logic circuits they control and output drivers are a major source of the noise generated from integrated circuits. When logic circuits switch state while driving a capacitive load, a rapid capacitor charging current flow generates an undesirable noise disturbance that is coupled to the integrated circuit substrate. The noise is typically coupled either by parasitic capacitive coupling between noisy circuits and the substrate or through direct connection of a power supply of a noisy circuit to the substrate. The load capacitances are undesired, but inherent in any circuit. The problem is multiplied since integrated circuits typically contain hundreds to hundreds of thousands of logic circuit gates that, when switched simultaneously, create extreme voltage transients that may upset other circuits.
One method for separating analog and digital circuits is by using a higher resistivity integrated circuit substrate. A higher resistivity substrate helps to electrically partition the integrated circuit substrate into quiet and noisy areas, separated by a relatively high resistive path. One problem with higher resistivity substrates is that noise is never completely separated since noise can still couple to common supplies. The noise may affect the operation of sensitive circuits. Another problem with this technique is that the trend is for high density, lower cost processes that use a low resistivity substrate. A low resistivity substrate does not allow effective separation of digital and analog noise for substrate partitioning. Furthermore, most integrated circuit fabrication companies require that logic grounds connect electrically to the substrate for reliability and robustness thus increasing noise to the substrate.
Using a low resistivity integrated circuit substrate also presents noise problems. One technique to reduce digital noise is by isolating the substrate noise from as many analog circuit components as possible by using an N-well. An N-well, however, does not allow total isolation of the digital noise from the analog circuit since some noise will always be capacitively coupled to and through the N-well. Further, some components must lie directly on the substrate and cannot make use of an N-well. Because isolation differs according to component structure, this technique always results in differing amounts of noise coupled to different parts of the analog circuit. The variances will be seen as a differential signal by the circuit. Another method for reducing noise coupled into analog circuits using a low resistivity integrated circuit substrate is robustly connecting the substrate to a good external ground with a low impedance path. One problem with such a method is that extra pins must be provided on the integrated circuit to connect to the external ground. Another problem is that the high frequency components of the switching circuits make it impossible to obtain a low impedance path to external ground through inductive bond wires and package lead frame in a cost effective way and without using many ground pins. Typically, spare pins are either not available or may require increasing the package size to accommodate these extra pins. This method may reduce the effects of noise significantly, but for highly sensitive circuits may not provide adequate noise reduction.
Another method for reducing noise effects is using fully differential circuits. Fully differential circuits are good at rejecting noise that is common to their inputs. Several problems exist in the employment of fully differential circuits. One problem is that when laying out a circuit it is hard to match the noise induced on its differential signal lines. For example, a mismatch of just a few fempto-farads of capacitive coupling between differential signal lines to a noise signal can impair the performance. Another problem with differential circuits is that in automotive applications differential circuits are not a typical functional requirement since they are more complex, more area intensive and thus, more costly than single ended circuits. Yet another problem is that the ability to reject common mode noise in differential circuits decreases with increasing noise frequency.
Another method for improving noise immunity is to sample when the noise has decayed sufficiently. Typical systems sample data just before a new clock edge and after sufficient quieting from the previous clock edge occurs. The problem with such a method is that for faster clock frequencies, typically more than 4 MHz (considered low by today""s standards), the substrate noise does not have time to sufficiently quiet during sampling and as technology advances clock frequencies will continue to increase.
Each of the methods described above reduces noise to a certain extent. Conventional thinking, however, is that separation or filtering of noise are the best methods to reduce the effects of noise. It is evident an improved method for eliminating the effects of noise would solve a long felt need.
The object of the invention is to enable analog or other noise susceptible circuits that share a common distributed electrical plane with digital or other noise generating circuits to achieve excellent noise immunity from noise induced on the plane. The present invention is a complete paradigm shift from prior art noise immunity solving methods.
The present invention has a distributed electrical plane and a reference electrical portion non-ideally coupled to the distributed electrical plane. Noise generating components are coupled to the distributed electrical plane and induce noise onto said distributed electrical plane. Noise susceptible components are also coupled to the distributed electrical plane. A coupling means for coupling the noise susceptible circuits to the distributed electrical plane more evenly distributes noise to the noise susceptible circuits so that the noise is common and indistinguishable throughout the noise susceptible circuits and the noise susceptible circuits operate with immunity to the noise.
By coupling noise from the distributed electrical plane (e.g., substrate of an integrated circuit) into the analog circuitry of an integrated circuit and coupling noise from the substrate into the analog inputs and outputs of the integrated circuit, the analog circuit acts as if no noise is present, since all the noise is common throughout the analog circuit.
One advantage of the present invention is substrate noise immunity is superior to other known methods of noise reduction. Another advantage is that noise reduction remains effective even at high noise frequencies where other techniques loose their ability to work and without the need for more costly integrated circuit packaging.